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Accuracy of Performance Counter Measurements

Accuracy of Performance Counter Measurements
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Conference Paper: ISPASS'09, April, 2009

Many experimental performance evaluations depend on accurate measurements of the cost of executing a piece of code. Often these measurements are conducted using infrastructures to access hardware performance counters. Most modern processors provide such counters to count micro-architectural events such as retired instructions or clock cycles. These counters can be difficult to configure, may not be programmable or readable from user-level code,
and can not discriminate between events caused by different software threads. Various software infrastructures address this problem, providing access to per-thread counters from application code. This paper constitutes the first comparative study of the accuracy of three commonly used measurement infrastructures (perfctr, perfmon2, and PAPI) on three common processors (Pentium D, Core 2 Duo, and AMD ATHLON 64 X2). We find significant differences in accuracy of various usage patterns for the different infrastructures and processors. Based on these results we provide guidelines for finding the best measurement approach.

@INPROCEEDINGS{Zaparanuks09, author={Zaparanuks, D. and Jovic, M. and Hauswirth, M.}, booktitle={Performance Analysis of Systems and Software, 2009. ISPASS 2009. IEEE International Symposium on}, title={Accuracy of performance counter measurements}, year={2009}, month=april, volume={}, number={}, pages={23 -32}, keywords={AMD ATHLON 64 X2;Core 2 Duo;PAPI;Pentium D;clock cycles;hardware performance counters;micro-architectural events;perfctr;perfmon2;performance counter measurements;performance evaluations;retired instructions;software infrastructures;user-level code;microprocessor chips;performance evaluation;software architecture;}, doi={10.1109/ISPASS.2009.4919635}, ISSN={}, }